C3-2 A 0.028mm2 19.8fJ/step 2nd-Order VCO-Based CT ΔΣ Modulator Using an Inherent Passive Integrator and Capacitive Feedback in 40nm CMOS

This paper presents an OTA-less 2nd-order VCO-based CT ΔΣ modulator featuring a passive integrator that makes use of the VCO’s inherent parasitic effect. A low-power capacitive feedback technique is also presented for robust loop compensation. Fabricated in 40nm CMOS, the prototype occupies 0.028mm2 of active area and consumes 524μW when sampling at 330MHz. The ΔΣM achieved peak Walden FoM of 19.8fJ/step with 68.6dB SNDR over 6MHz BW. Introduction Traditional CTΔΣMs require high gain OTA in the loop filter, thus facing severe challenges due to reduced intrinsic gain and voltage headroom in advance process nodes. To circumvent this issue, CTΔΣMs employing ring VCO as integrator and quantizer have been reported in [1]-[6]. They leveraged the highly digital and intrinsic multi-level quantization nature of the ring VCOs, bestowing improvement in scaling-friendliness and power efficiency. Nevertheless, the mostly-digital/OTAless architectures were limited to only 1st-order ([1]-[3]), while OTAs were required to achieve higher order ([4]-[6]), and thus deemphasizing the benefits brought by the VCO. Apart from VCO-based techniques, CTΔΣMs using passive loop filters have been demonstrated as an alternative solution to scaling friendliness [7]-[8]. But they rely on the highly non-linear nature of 1-bit quantizer to provide loop gain, thus losing the bandwidth efficiency feature of multi-bit quantization. This paper presents an OTA-less 2nd-order VCO-based CTΔΣM featuring an inherent passive integrator and a low-cost capacitive feedback technique for loop compensation. It makes use of the inherent input parasitic of the current-starved VCO (CCO) as a passive integrator, at the same time harnesses the vast CCO tuning gain readily available in scaled process, implementing 2nd-order shaping with multi-bit quantization using only passive and highly digital components. This work combines the respective key merits of VCO-based and passive architectures, thus demonstrating substantial improvement in scaling-friendliness compared to existing high order VCObased CTΔΣMs involving OTAs. The prototype chip fabricated in 40nm achieved Walden FoM below 20fJ/step. Proposed 2nd-order VCO-based CTΔΣM Unlike active-RC integrators whose integration behavior is highly subject to the GBW of the OTA, CCO integrators, who operates through the inherent frequency-phase integration, are defined solely on the I-F tuning gain KCCO. In a linearized CCO model, KCCO depends majorly on node capacitance, suggesting that high integration gain and bandwidth can be achieved simply by process scaling with little power penalty. This key advantage can be maximally harnessed by making the frontend loop filter passive and have the loop gain supported solely by the CCO. By doing so, the power contributed to increasing loop order is minimized. Although a leaky front-end will render non-ideal noise shaping, as long as the passive poles are placed in band, the degradation in SNDR is insignificant. The top-level architecture of the proposed 2nd-order CTΔΣM is shown in Fig.1(a). It contains a 1st-order fully passive loop filter, followed by a 15-stage CCO-based integrator and quantizer. This work employs a phase extended quantizer which provides resolution doubling and tri-level DAC control with great power efficiency [3]. RDAC is adopted as resistors exhibit lower noise and better matching. DEM logic is omitted as it is implemented intrinsically by the dual-CCO structure. Instead of explicitly introducing extra RC network, this work proposes to form a passive integrator right at the CCO input node with components inherently presented in the circuit: the loading effect from the DAC, input V-I resistor Rin, and the parasitic effect of the CCO input (Fig. 1(b)). The CCO input parasitic LPF is inherently a passive integrator, but was usually undesired and detrimental to stability. In prior works, this parasitic pole had to be desensitized by either introducing extra feedforward ([4], [5]) or ensuring low impedance at the control node [6], which leads to hardware or power overhead. In this work, this parasitic effect is in turn utilized as a key element to the passive first stage, such that this undesired pole is absorbed into the NTF and contributes to the 2nd-order shaping, eliminating the need for parasitic cancellation. Furthermore, as all noise generating components of the passive integrator are inherent regardless the integrator being formed or not, little noise penalty is introduced by the passive first stage. The only extra hardware required is the capacitor CM, which is used to modified the pole location of the passive integrator. CM is made with tunable MOSCAPs for maximum area efficiency. Nonlinearity of CM is negligible as the signal component on the CCO input node is only about 10 mVp-p. As the passive integrator merged closely with the CCO quantizer, conventional CIFF or CIFB structure cannot be implemented directly. To stabilize the 2nd-order ΔΣM, a lowcost capacitive feedback technique is proposed. As depicted in Fig. 1(b), a capacitor is connected in parallel with each DAC resistor. This technique utilizes the analog differentiator nature of a capacitor, and is highly hardware efficient as no additional logic, driver or timing is required other than the capacitors. At high frequency, the phase lead introduced by the feedback capacitors bypasses the phase lag of the passive integrator, acting as a secondary feedback path that restores phase margin. Under tri-level control scheme, the extra power drawn by these feedback capacitors can be proven very low. Fig. 2 depicts the charge flow in the capacitors during different input transition cases. The feedback caps only draw energy during rising transitions (i.e. 0 to 1 or -1). By biasing the CCO at appropriate center frequency where DAC transition density is minimized, e.g. near multiples of fs/2, the overall power consumed by the capacitive feedback can be further reduced(Fig.3(a)). Behavior simulation (Fig. 3(b)) shows that the extra power required is lower than 10uW with Ibias≈55uA, where fcco≈0.49*fs. As the loading effects of the RDAC, capacitive feedback and the passive integrator are mutually coupled, these 3 blocks must be designed concurrently for optimum result. The equivalent network of these blocks is shown in Fig. 4(a). The DAC inputs can be combined as a single equivalent input VDout. The s-domain transfer function of the passive loop filter Hn(s), defined as ICCO/VDAC, can be derived, and subsequently the NTF can be obtain by impulse invariance method. As RF is C3-2